Optimizing Flip Chip Packaging for High Density Bump via Mold Flow Simulation with Through-Holes

Flip-chip packaging techniques have become essential for electrical components, particularly in fine-pitch packages where bump sizes are small and high density under the chip. These techniques enhance thermal performance and bump connections while addressing concerns about mold voids. However, the high bump density and limited pitch in flip-chip techniques will lead to potential defects, including mold voids. To efficiently reduce voids, incorporating an extra runner in the package for void venting is one effective solution. This study investigates the effects of through-hole size, molding resistance, and mold flow performance using an advanced methodology. This methodology considers govern equations such as the viscosity model, curing reaction, and Finite Element Method (FEM) analytical method, with a focus on the structure design to predict or evaluate defects occurring in molding process, particularly mold voids and the weld risk. One of the major challenges in this approach is controlling the distance and density of bump pitches on the substrate of bonded spheres while attached spheres to package. The results demonstrate that a through-hole size of 0.2mm exhibits better performance in terms of potential mold voids with 44 units per strip, and 68 units for a 0.3mm through-hole size. Melting behavior under chips for void venting was clearly observed in specific areas. Additionally, the filling percentage, influenced by flow status, can be used to predict the mold flow risk. Base on FEM analytical, structure modification, and recipe optimization, the risk areas or positions can be identified and mitigated during the substrate or layout process. The adoption of high-density bump technology has significantly advanced our packaging process, particularly as devices become smaller, especially in the case of safety devices where reliability and testing are subject to harsh conditions. Even packages with micro voids undergo rigorous testing procedures to ensure optimal performance and reliability.