Design of a Low Dropout Voltage Regulator (LDO) Using SCL 180nm CMOS Technology

This paper proposes the design of a low dropout voltage regulator (LDO), simulated using SCL 180nm technology in Cadence design tool. It regulates an output voltage of 1.3V from a supply voltage of 1.8V with a reference voltage of 1.8V. Various corner checks are performed over a temperature range from -40°C to 125°C with a VDD variation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 10\%$</tex>. The gm/Id methodology is employed in this design to ensure that all transistors operate in the saturation region.

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Publication Details

Published
2024-12-06
DOI
https://doi.org/10.1109/isense63713.2024.10872390
Citations
4
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
0.83
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article

Design of a Low Dropout Voltage Regulator (LDO) Using SCL 180nm CMOS Technology

M R Roshna, V R Adersh
4 citations
Low-power high-performance VLSI design
0.83
article

Design of a Low Dropout Voltage Regulator (LDO) Using SCL 180nm CMOS Technology

M R Roshna, V R Adersh
article en
4 citations

Abstract

This paper proposes the design of a low dropout voltage regulator (LDO), simulated using SCL 180nm technology in Cadence design tool. It regulates an output voltage of 1.3V from a supply voltage of 1.8V with a reference voltage of 1.8V. Various corner checks are performed over a temperature range from -40°C to 125°C with a VDD variation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 10\%$</tex>. The gm/Id methodology is employed in this design to ensure that all transistors operate in the saturation region.

Affordable and clean energy
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Low-power high-performance VLSI design
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Design of a Low Dropout Voltage Regulator (LDO) Using SCL 180nm CMOS Technology — M R Roshna, V R Adersh · (2024) | TGRS Research Map | TGRS