UVM Verification of AXI-Lite Sram Controller

Memory controllers, which oversee essential storage and cache functions for system functionality, are vital parts in Central Processing Unit (CPU) and System-on-Chip (SoC) architectures. Flaws in their architecture could lead to significant reduction in performance or even system failure. Advanced eXtensible Interface Synchronous Random Access Memory (AXI SRAM) controllers are important components in this domain known for their ability to enable high-speed memory operations, which guarantees reliable memory management in SoC's. Considering the vital role they perform, a thorough verification procedure is necessary to ensure perfect operation and uncompromising dependability. This work focuses on the comprehensive testing of an AXI-Lite Synchronous Random Access Memory (SRAM) controller and the creation of environment based on the Universal Verification Methodology (UVM). UVM works in tandem with System Verilog to create a reliable and scalable verification environment is the most reliable means of expressing the verification of SRAM controller. A thorough testing strategy is made possible by utilising this verification method, which simulates various scenarios and generates random address and data packets to find possible design flaws. Through this contraption we were able to create a verification framework that included scoreboard, monitor, and driver that were all coordinated to enhance and automate the verification process. Because of UVM's inherent capacity to generate data sets automatically, a wide range of potential scenarios are covered, which improves efficiency and provides comprehensive coverage reports. We implemented a Master obeying AXI - Lite protocol in UVM driving the controller as the slave. Our verification efforts yielded 96% overall coverage, demonstrating the reliability of the AXI - Lite SRAM controller for deployment in high performance systems.