Performance Analysis of 64-bit and 32-bit Shakti Core Implementations

In this paper, the cores of Shakti Vajra and Parashu SoC, i.e., C-Class and E-Class, are synthesized using the Cadence Genus tool. A set of user-defined constraints are given as input to the tool in order to generate the netlist and their corresponding performance analysis reports. The main focus of this paper is to compare the performance of the cores using power, area and timing parameters. The scope of this study uses scl pdk 180nm manufacturing technology at 100MHz frequency. The cores were designed using Bluespec System Verilog (BSV) language, which was converted to verilog code using the Bluespec Compiler (BSC).