Approximate Convolution on FPGA Using Multipliers Based on 4:2 Compressors

Multiplication is one of the key operations required in real-world complex scenarios. One of its key usage is in convolution operation which is the prominent step in signal processing and deep learning algorithms like Convolutional Neural Networks (CNN). These operations require large resources, area and power to operate. Approximation is one of the techniques used for solving such problems. Approximation provides us with the advantage of using less resources, time, power and computation by giving the results with an acceptable accuracy. Field Programmable Gate Arrays (FPGAs) are hardware platforms, which provide better power consumption and are easily re-configurable. Here, we present an inexact multiplier using a 4:2 approximate compressor with six gates and perform convolution operation of 64×64 input matrix with a 3×3 kernel matrix using the approximate multiplier. The convolution architecture proposed here is implemented on Virtex Ultrascale+ FPGA with an operating frequency of 150 MHz. Error analysis is performed and is compared with the existing architectures. An accuracy of 95 % has been achieved by the proposed architecture.