Synthesis and Place and Route of the OR1200 Processor:A Detailed Implementation

This paper presents a study on the synthesis and Place and Route (PNR) of the OR1200 processor, an open-source RISC architecture. Using the Genus and ICC2 Compiler tool suite, we optimized the OR1200 design to meet stringent timing, area, and power constraints. The synthesis involved configuring design constraints and generating a gate-level netlist, followed by a comprehensive PNR workflow, including floorplanning, placement, and routing. We address key challenges such as congestion management and timing closure, and provide an analysis of final design metrics, showing significant improvements. This study highlights the effectiveness of advanced EDA tools in optimizing open-source processor designs and offers insights for future digital design projects.