Mitigation of Self-Heating by Buried Oxide Engineering in Sub-5-nm GAA Nanosheet FETs

Triple-stacked sub-5-nanometer gate-all-around nanosheet field-effect transistors show great promise as next-generation nanoscale electronics devices, however, they face significant challenges due to the self-heating. This paper illustrates how buried oxide engineering can help reduce self-heating in three-dimensional nanoscale devices. We compare the performance of silicon-compatible materials such as SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, Al<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>, and AIN with high thermal conductivity as buried oxide materials to investigate the effects of self-heating. Our findings demonstrate improved performance and reduced power dissipation in the stacked nanosheet transistor with a buried oxide layer.