Investigation of Gate-Length Scaling Effects on the Thermal Reliability of 25T-TSPC Flip-Flop

This paper presents 25T-TSPC-FF (25-transistor true signal-phased-clock flip-flop), with the analysis of gate-length scaling effect at 16-nm, 22-nm, and 32-nm CMOS technology and voltage scaling for different V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> scaling at 0.7/0.8/0.9/1.0/1.1/1.2V for different temperature from 27°C to 107°C. The temperature effect on the suggested FF shows that as the gate length increases from l6nm to 32nm the power consumption and delay increases for the wide range of operating temperature. For the gate length scaling the power consumption decreases and delay increases as the temperature increases from 27°C to l07°C. for the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>- scaling done on the 16-nm CMOS technology for the different supply voltage of 0.7/0.8/0.9/1.0/1.1/1.2V the delay decreases and power consumption increases as the voltage increases from 0.7V to 1.2V. As the effect of temperature on V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>-scaling delay and power consumption increases as the temperature increases from 27°C to l07°C. The approximate delay is about 1ns.