Thermal Reliability Study of Aggressively Scaled C2SFF for Future IoT Applications

This paper presents the C2SFF (contention-free change-sensing Flip-Flop), with the thermal reliability analysis on different gate length scaling and voltage scaling(VDD) of 16nm/ 22nm/32nm and respectively. The spice simulation is done using the 16nm CMOS technology with different supply voltage at wide range of operating temperature. From the analysis we observed that as the temperature increases from 27°C to 107°C power consumption decreases and delay increases for different gate-lengths. The thermal effect on the Von-scaling shows that as the VDD increases from 0.7V to 1.2V power consumption increases and delay decreases. From the analysis of power-delay product (PDP) on C2SFF as the gate length decreases from 32nm to 16nm, PDP decreases with approximately 80% at different temperature. At the different Von-scaling, PDP decreases as the temperature increases at different supply voltage from 0.7V to 1.2V.