Design and Implementation of 64 Bit SRAM and SDRAM Controller in SCL 180nm

This paper details the design and implementation of a 64-bit SRAM and SDRAM controller using the SCL 180nm technology node, utilizing Cadence Genus for synthesis and Cadence Innovus for the Place-and-Route (PnR) process. The objective is to create high-performance, reliable memory controllers optimized for integration in advanced semiconductor designs. The 64-bit SRAM controller is crafted to deliver rapid access times and robust data integrity, crucial for applications requiring fast and reliable memory. In parallel, the 64-bit SDRAM controller is designed to efficiently manage dynamic memory operations, supporting features such as burst transfers, auto-refresh, and error correction, essential for maintaining high data throughput and system stability. During implementation, Cadence Genus is employed for logic synthesis, converting the high-level design into an optimized gate-level netlist. This synthesis process ensures the design adheres to the specific timing, area, and power constraints of the SCL 180nm technology. The subsequent PnR process with Cadence Innovus involves precise placement of the controllers, incorporating I/O padding to enhance signal integrity and connectivity. Critical steps such as clock tree synthesis and routing are executed to minimize clock skew and establish efficient data paths. Validation and verification encompass rigorous testing protocols to confirm that the controllers meet all design specifications and industry standards. The successful development of the 64-bit SRAM and SDRAM controllers underscores the viability of implementing high-performance memory solutions within the SCL 180nm technology node, paving the way for future advancements in semiconductor technology. The study compares power and area analyses using the SCL180nm technology library. Our design achieved an area of 2,899,361.5 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>and power efficiency of 0.01001 nW pre-CTS, and an area of 2,900,380.7 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -with 0.01039 nW in post-route, showing competitive performance.