RT-DBR: Dynamic Bandwidth Reservation for Real-Time Application on CPU-GPU Heterogeneous SoC

When heterogeneous cores concurrently access shared memory, severe bandwidth contention limits data transmission, increases memory access latency for tasks, disrupts the predictability of real-time application execution, and affects system responsiveness. To address these issues, this paper proposes a dynamic bandwidth regulation mechanism based on core memory access patterns (RT-DBR). This mechanism enables fine-grained adjustment of core memory access request scheduling rate through the memory controller. Furthermore, it operates transparently to the application programs on the cores, effectively reducing system interruptions caused by bandwidth regulation. Experimental results demonstrate that the RT-DBR can effectively alleviate unnecessary bandwidth contention caused by bursty memory accesses and ensure real-time performance of programs.