Gate engineering solutions to mitigate short channel effects in a 20 nm MOSFET

• A new dielectric gate architecture MOSFET is presented to improve MOSFET performance. • High-K dielectric material (HfO 2 ) is used for oxide gate, which significantly reduces quantum mechanical tunneling and gate leakage current, enabling continued device scaling. • Silvaco ATLAS simulator has been used to analyze the characteristics of structures. This work presents a promising approach to addressing scaling challenges in advanced MOSFET technology. It proposes a novel MOSFET structure designed to enhance electrical performance by introducing asymmetry in the gate dielectric thickness. In the proposed design, the gate dielectric consists of a high-k material (HfO₂), with the oxide layer on the source side being three times thicker than that on the drain side. Using TCAD Silvaco simulations, the impact of this gate dielectric architecture on key parameters including threshold voltage, subthreshold swing, and gate leakage current was analyzed. The results demonstrate that the asymmetric dielectric design significantly enhances device performance, achieving a ∼12% reduction in leakage current, a 13% increase in ON current, and a subthreshold swing of ∼ 66 mV/dec. Furthermore, the non-uniform electric field distribution improves control over the pinch-off point and enhances immunity to short-channel effects.