Compensated Current Mirror Neuron Circuits for Linear Charge Integration with Ultralow Static Power in Spiking Neural Networks

Spiking Neural Networks In article number 2400673, Jonghyuk Park, Sungjoon Kim, and Woo Young Choi present a neuron circuit that optimizes vector-matrix multiplication performance in spiking neural networks (SNNs) while ensuring low-power consumption. This research validates the achievement of high SNN system accuracy through a CMOS neuron circuit arranged to prevent non-linear operations that occur during the integration of massive synaptic arrays and neurons.