Frequency Compensation of Three-Stage Amplifier with Self-Cascode Structure and DTMOS Transistor with Active LHP Zero Circuit

This paper addresses the frequency compensation in a three-stage amplifier for a large capacitive load of 1[Formula: see text]nF. The proposed circuit-1 uses a Self-Cascode (SC) structure in the first stage and an active left-half-plane (LHP) zero circuit at the output of the second stage to cancel the parasitic pole. A Miller capacitor and resistor are also employed in the outer loop to solve the Right Half Plane (RHP) zero issue. A DTMOS transistor along with SC is used in the proposed circuit-2 for enhancing the gain-bandwidth product (GBW). Additionally, a feed forward path is employed to improve the large signal response. The functionality and performance of the proposed amplifiers is examined using TSMC 0.18[Formula: see text][Formula: see text]m CMOS process in Tanner tool. The proposed amplifiers show a maximum GBW, minimum phase margin, and slew rate of 5.2[Formula: see text]MHz, 60 ∘ and 0.1[Formula: see text]V/[Formula: see text]S, respectively. The maximum Common Mode Rejection Ratio (CMRR) and Power Supply Rejection Ratio (PSRR) are observed to be 236[Formula: see text]dB and 84.8[Formula: see text]dB, respectively. To confirm the robustness of the proposed amplifiers, corner analysis has also been done.