Die Placement Process Optimization in Reducing Occurrence of Solder Short between Flip-Chip Die Pad

This study investigates the occurrence of solder shorts in a new System-in-Package (SiP) product during the setup phase in Inari, specifically related to a flip-chip die with a tighter solder bump pad pitch. Despite no abnormalities in the employed processes, an increasing number of solder shorts were observed. The study details a series of process optimizations conducted to restore the yield to an acceptable level. Within the SMT processes, certain process parameters, including those related to solder printing, flip-chip die placement, and solder paste reflow, were identified as potentially contributing to the solder short occurrences. Various evaluations and optimizations were performed, ruling out most variants and pinpointing the impact speed parameter setting during die placement as a significant factor influencing solder short incidence between flip-chip die pads.