Automotive High Power Flip Chip Quad Flat No-leads Package Robustness Study
FCQFN (Flip Chip Quad Flat No-leads) package is common for automotive high power products in electronics industry especially for thermal efficiency. Although the packaging process is not complicated and it has thinner body size than the traditional wire bond QFN package, there are some challenges in the packaging development. Among the challenges that can affect the final performance of the package, delamination is a common one. Therefore, in this study, the investigation of the delamination behavior in automotive high power FCQFNs is conducted to identify the delamination mechanism. The package size of FCQFN in this study is 5*5 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The chip is connected to the Ag-plated pad of the metal lead by Cu pillar bump and encapsulated by mold compound to provide physical protection. The package performance was validated by MSL3 (Moisture Sensitivity Level 3) and thermal cycling upto 2000 cycles. During early development stage, Through-scan results showed obvious delamination which concentrated at die paddle areas with shorter half etching and without tie bar. Moreover, the cross-sectional results showed the delamination occurred between die paddle sidewall and mold compound. In addition, thermal mechanical modeling indicated the high stress area at delamination position. The stress reduction was predicted by modeling and verified by empirical result. Based on the experimental results, delamination can be significantly improved by increasing die paddle half etching width which is a simple and breakthrough solution. Finally, the delamination mechanism is concluded to be insufficient contact area between short etched die paddle and mold compound. The die paddle with longer half etching width design has shown to be greatly effective in mitigating the risk of delamination, hence ensuring a robust automotive high power FCQFN package.
Authors
- Wen Yuan Chuang
- Fei Li (ORCID: https://orcid.org/0000-0002-4695-944X)
- Wen Hung Huang
- Eu Poh Leng
- A. Tsai
- Daisuke Hosoda
Institutions
- Advanced Semiconductor Engineering (Taiwan) (TW)
Publication Details
- Published
- 2024-10-16
- DOI
- https://doi.org/10.1109/iemt61324.2024.10875080
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00