New Enhanced Loop Formation for Compute DRAM Package: An Innovative Solution to Enhance Robustness of Wire Loop and Enable Design Rule Limitation

The extend of this paper covers Compute DRAM (Dynamic Random Access Memory) package with the single DRAM die attached in a BOC (board on chip) package. In this package the lead is located above the die, thus a relatively high loop will be required. This condition is set to avoid the wire-to-lead short due to the insufficient gap. In addition, die placement become a concern by which offset of the die placement increases the risk of wire touching the adjacent lead, which violate the wire bond design rule. Standard loop is unable to support a high loop as it will result in wire sweep. Hence, the PSL (Power Series Low) loop is an innovative approach to enable the design rule limitation by increasing the wire loop height in a stable condition which no sign of stress at ball neck and zero wire short reject.