An Innovative Approach to Scanning Acoustic Microscopy (SAM) for Layered Structures in Wafer Level Chip Scale Package (WLCSP)
This technical paper introduces an innovative approach aimed at overcoming the limitations associated with conventional Scanning Acoustic Microscopy (SAM) techniques in the analysis of Wafer Level Chip Scale Packages (WLCSP). Conventional SAM methods have struggled to fully characterize interfaces within these packages, requiring complex setups with multiple frequency transducers and resulting in limited scanning, especially for Printed-Circuit-Board (PCB) mounted units. A new method to apply 200 MHz UHF (Ultra-High Frequency) transducer for single scanning of multiple layers for both loosen and PCB mounted units are presented in this work. There is currently technique performs a single scan from top to bottom to capture many layers of interfaces in stacked materials. This approach facilitates comprehensive data acquisition across all layers within the WLCSP, especially for PCB mounted. By acquiring information of material factors for specific layers following the properties to derive acoustic impedance, the phase inversion of waveforms can be obtained. Subsequently, step to estimate the gate location is performed on the corresponding interface of interest. Repetitive analysis on SAM and comparative analysis on cross section is carried out to ensure the gate location is positioned accurately between boundary of each material interface. Through rigorous comparative analysis with conventional methods, the outcome of this work demonstrates superior time efficiency while maintaining data integrity and ensuring comprehensive coverage for WLCSP. This proposed technique is expected to overcome the limitations of conventional approaches employed for scanning layered structures in WLCSP.
Authors
- Mohd Faizairi Nor
- Mohd Zaid Abdullah (ORCID: https://orcid.org/0000-0002-5747-9812)
- P.K. Vijayan (ORCID: https://orcid.org/0000-0002-9784-5784)
- Subashini Periasamy
Institutions
- Nexen (Canada) (CA)
Publication Details
- Published
- 2024-10-16
- DOI
- https://doi.org/10.1109/iemt61324.2024.10875212
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00