Novel Bond-Wire Optimization Method for PISI and Yield Improvement

With technology shrinking and increasing device functionality, device power and performance imposes major challenges to meet overall system level electrical specification. These electrical specifications such as PISI, EMI/EMC, IR Drop, PDN Impedance, I/O interface timing, BOM cost etc. play important part in Die-PKG-PCB Co-design for complex SoC having high-speed interfaces designed for different applications. In this paper, we propose a novel bond-wire optimization method in the wire-bond package to reduce Power-Ground (PG) pins. Reducing PG pins can provide more signal pins for customer application and reduce PG pads at die level to optimize die size for complex SoC having high-speed interfaces to meet overall electrical specifications and yield. PG pads at die are connected to PG ring/bar and ground flag which are connected to package pins. Bond-wire connected from isolated ring to package pin is called jumper wires. These jumper wires are required to reduce package parasitics (Resistance (R), Inductance (L) and Capacitance (C) to meet electrical specification. However, jumper wire bonding can impose manufacturing challenges during assembly. An example was seen with a high volume manufacturing product which has high package yield loss (~1000ppm). In this paper, jumper bond-wire optimization with an evaluation vehicle is presented to improve the package yield loss and at the same time meeting the overall system level electrical specifications for the complex SoC.