Wafer Level Plasma as An Alternative for Wafer Pre Thin Process

As the memory industry continue to evolve and grow with market size valued at USD 104.58 billion in 2022 and the worldwide semiconductor memory market is expected to reach USD 201.91 billion by 2032, simultaneously the industry continues to grow with the complexity of new wafer tech nodes with requirements of thinner die based on the demanding application needs of higher storage and processing capacity of single chip. This fuels the requirement to venture into SDBG (Stealth Dicing Before Grinding) process as it provides solution of increased in the number of dies per wafer due smaller saw street requirements and improved die strength which plays an important role for thin die application. The wafer Pre-Thinning process log point is unique to Micron application of the SDBG, this is a requirement as currently backend assembly wafers are received with backside film which is not removed during the wafer fabrication process at front end. The removal of the film is vital for the SDBG as it impacts the laser penetration during the stealth dicing process. This paper fully explores wafer level plasma (Fig 1) as an alternative method in the backside film removal rather than using mechanical grinding to remove the backside film. This paper also collects the feasibility data of such applications.