Development of Panel Level Packaging for Multi-Chip Modules with High-Precision Redistribution Layer

The swift progression of artificial intelligence, particularly exemplified by the recent advancements in ChatGPT, necessitates markedly increased data transfer rates. Among the advanced packaging techniques, Fan-Out Multi-Chip Module (FOMCM) technology is distinguished by its cost-effectiveness and high-speed data transmission capabilities. FOMCM manufacturing is produced at the wafer level for sizes up to 12 inches (300 mm). To further enhance productivity and reduce costs, the transition to larger form factors is under investigation. The panel dimensions considered in this shift range from 300x300 mm to 510x515 mm, and potentially up to 600x600 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.This paper demonstrates the development of a Chiplet package using panel-level FOMCM technology. The designed package has dimensions of 65x65 mm and includes four integrated dies. These dies are mounted onto three pre-fabricated redistribution layers (RDLs) using the Flip-chip (FC) technique, executed on a glass panel measuring 510x515 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Furthermore, this study addresses the primary challenges encountered in panel-level packaging (PLP), such as warpage, and die shift, and provides insights into overcoming these obstacles.