Design of Delay Unit for Synchronizing EEG Signal with FPGA-based Hardware Accelerator

The technology used for processing EEG signals from the brain for a specific application is called the brain-computer interface (BCI). This method has numerous applications as a non-intrusive signal capture technique. Hardware accelerators are used to implement an accurate and stable system for capturing these lowfrequency signals, as EEG signal acquisition is highly sensitive, particularly in seizure detection. A critical challenge in this integration is precisely synchronizing EEG signals with the hardware accelerator to ensure real-time processing and accurate detection of epileptic seizures. Detecting a seizure from an EEG signal requires collecting much data from the brain's electrical activity. The general performance of the CPU is not enough to handle this massive data. So, the proposed system used FPGAs (Field-Programmable Gate Arrays) family Zynq 7000 series as a hardware accelerator. FPGAs offer the designer the benefits of custom hardware design, eliminating costly development expenses and time-consuming production processes. This article aims to propose a VLSI design using built-in IP cores provided by Xilinx and evaluate an EEG delay system that can synchronize the built memory of FPGA with the real-time data acquired from brain signals. The Experimental results demonstrate that the proposed approach enables the creation of a controllable delay platform with a minimum delay step of less than 1ns and a maximum delay time exceeding 200us, compared to skew, resulting in the efficacy of the delay unit in providing seamless synchronization, enhancing the overall performance of the EEG-based seizure detection system. The post-synthesis estimated power is 134mW, a setup time of 0.420nS, and a hold time of 5.713nS.