A Compact Low-Power Chopper Low Noise Amplifier for High Density Neural Front-Ends

This paper presents a low-power and area-efficient chopper-stabilized low noise amplifier (CS-LNA) for in-pixel neural recording systems. The proposed CS-LNA can be used in a multi-channel architecture, in which the chopper mixers of the LNA are exploited to provide the time division multiplexing (TDM) of several channels, while reducing the flicker noise and rejecting the Electrode DC Offset (EDO). A detailed noise analysis including the effect of the chopper stabilization on flicker noise, and a design flow to optimize the trade-off between input-referred noise and silicon area are presented, and utilized to design the LNA. The adopted approach to reject the EDO allows to tolerate an input offset of ±50 mV, without appreciably affecting the CS-LNA performance, and does not require an additional DC Servo Loop (DSL). The proposed CS-LNA has been fabricated in a 0.13 μm CMOS process with an area of 0.0268 mm², consuming about 2 μA from a 0.8 V supply voltage. It achieves an integral noise of 4.19 μVrms (2.58 μVrms) from 1 to 7.5 kHz (from 300 to 7.5 kHz) and results in a noise efficiency factor (NEF) of 2.63 (1.62). Besides achieving a maximum gain of 38.67 dB with a tuning range of about 12 dB, the neural amplifier exhibits a CMRR of 67 dB. A comparison with the recent literature dealing with in-pixel amplifiers shows state-of-the-art performance.