A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling

The zoom ADC can achieve high resolution with low power by a coarse-fine architecture, but its bandwidth is very limited due to oversampling during the fine <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> conversion. This paper presents a single-sampling incremental zoom ADC. It addresses the fundamental bandwidth limitation by obviating oversampling while still retaining the merit of noise shaping. It also realizes the efficient three-step conversion with a highly hardware-reused architecture. A prototype ADC is implemented in 28 nm CMOS process. Operating under 5 MS/s sampling rate and 0.9-/1.8-V dual power supplies, it measures 89.5 dB signal-to-noise-and-distortion ratio (SNDR) and 93.4 dB dynamic range (DR) with 2.5 MHz bandwidth while consuming 2.36 mW power and occupying 0.19 mm2 area. Overall, this work achieves the competitive SNDR-based Schreier FoM of 179.7 dB and DR-based Schreier FoM of 183.6 dB.