Comprehensive Study of Electric Field and Subthreshold Drain Current in Junctionless Double-Material CSG Nanowire Transistors

A subthreshold drain current model has been developed for a Cylindrical Gate-All-Around (GAA) Junctionless Transistor with two distinct gate materials. This design incorporates two gate regions, each with different work functions, to effectively mitigate short channel effects arising from quantum mechanical phenomena. The electic field and drain current equation is derived for subthreshold regions to analyze the leakage characteristics of the device and to minimize the sources of leakage and static power consumption. The double-material gate structure is found to significantly enhance the transport efficiency of the device with control gate. The proposed analytical model is validated through comparisons with Sentaurus TCAD numerical simulations, showing strong agreement.