Design and FPGA Implementation of an Efficient Squarer Circuit Using Reversible Logic

This paper presents the design and FPGA implementation of an efficient 4×4 squarer circuit using reversible logic. The proposed architecture is developed using the hardware description language Verilog and synthesized with Xilinx Vivado and Xilinx ISE 14.7 tools. The FPGA implementation of proposed design has been done on Artix 7 (NexysA7). The main improvements in this work include a significant reduction in garbage output, quantum cost, and total reversible logic implementation cost (TRLIC) compared to existing designs. Notably, the proposed architecture achieves quantum cost and TRLIC reductions of 84.34% and 82.10%, respectively. The circuit also demonstrates a remarkably low delay of 1.076 ns, making it suitable for high-speed applications.