A 0.53-<i>μ</i>W/channel calibration-free spike detection IC with 98.8-%-accuracy based on stationary wavelet transforms and Teager energy operators

<i>Objective</i>. The brain-computer interface is currently experiencing a surge in the number of recording channels, resulting in a vast amount of raw data. It has become crucial to reliably detect neural spikes from a large population of neurons in the presence of noise, in order to constrain the transmission bandwidth.<i>Approach</i>. We investigate various time-frequency analysis methods for spike detection, followed by an exploration of energy operators amplifying spikes and signal statistics for adaptive thresholding. Subsequently, we introduce a precise and computationally efficient spike detection module, leveraging stationary wavelet transform (SWT), Teager energy operator, and root-mean-square calculator. This module is capable of autonomously adapting to different levels of noise. The SWT effectively eliminates high-frequency noise, enhancing the performance of the energy operators. The hardware computational process is simplified through the use of the lifting scheme and a channel-interleaving architecture.<i>Main results</i>. We evaluate the proposed spike detector with adaptive threshold on the publicly available WaveClus datasets. The detector achieves an average accuracy of 98.84%. The application-specific integrated circuit (ASIC) implementation results of the spike detector demonstrate an optimized interleaving channel of 8. In a 65 nm technology, the 8-channel spike detector consumes a power of 0.532<i>μ</i>W Ch<sup>-1</sup>and occupies an area of 0.00645 mm<sup>2</sup>Ch<sup>-1</sup>, operating at a 1.2 V supply voltage.<i>Significance</i>. The proposed spike detection processor offers one of the highest accuracies among state-of-the-art spike detection methods. Importantly, the ASIC explores the considerations in the scalability and hardware costs. The proposed design provides a systematic solution on spike detection with adaptive thresholding, offering a high accuracy while maintaining low power and area consumptions.

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Publication Details

Journal
Journal of Neural Engineering
Published
2025-02-13
DOI
https://doi.org/10.1088/1741-2552/adb5c4
Citations
1
Primary Topic
EEG and Brain-Computer Interfaces
Type
article
Field-Weighted Citation Impact
1.43
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article

A 0.53-μW/channel calibration-free spike detection IC with 98.8-%-accuracy based on stationary wavelet transforms and Teager energy operators

Zhining Zhou, Zichen Hu, Hongming Lyu
1 citations
Journal of Neural Engineering
EEG and Brain-Computer Interfaces
1.43
article

A 0.53-μW/channel calibration-free spike detection IC with 98.8-%-accuracy based on stationary wavelet transforms and Teager energy operators

Zhining Zhou, Zichen Hu, Hongming Lyu
article en
1 citations

Abstract

<i>Objective</i>. The brain-computer interface is currently experiencing a surge in the number of recording channels, resulting in a vast amount of raw data. It has become crucial to reliably detect neural spikes from a large population of neurons in the presence of noise, in order to constrain the transmission bandwidth.<i>Approach</i>. We investigate various time-frequency analysis methods for spike detection, followed by an exploration of energy operators amplifying spikes and signal statistics for adaptive thresholding. Subsequently, we introduce a precise and computationally efficient spike detection module, leveraging stationary wavelet transform (SWT), Teager energy operator, and root-mean-square calculator. This module is capable of autonomously adapting to different levels of noise. The SWT effectively eliminates high-frequency noise, enhancing the performance of the energy operators. The hardware computational process is simplified through the use of the lifting scheme and a channel-interleaving architecture.<i>Main results</i>. We evaluate the proposed spike detector with adaptive threshold on the publicly available WaveClus datasets. The detector achieves an average accuracy of 98.84%. The application-specific integrated circuit (ASIC) implementation results of the spike detector demonstrate an optimized interleaving channel of 8. In a 65 nm technology, the 8-channel spike detector consumes a power of 0.532<i>μ</i>W Ch<sup>-1</sup>and occupies an area of 0.00645 mm<sup>2</sup>Ch<sup>-1</sup>, operating at a 1.2 V supply voltage.<i>Significance</i>. The proposed spike detection processor offers one of the highest accuracies among state-of-the-art spike detection methods. Importantly, the ASIC explores the considerations in the scalability and hardware costs. The proposed design provides a systematic solution on spike detection with adaptive thresholding, offering a high accuracy while maintaining low power and area consumptions.

Journal of Neural EngineeringVol. 22(2)
ShanghaiTech University (CN), Shanghai Customs College (CN)
Affordable and clean energy
Openalex Percentile: Top 23%
EEG and Brain-Computer Interfaces
1.43
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