A Transient Enhanced Capacitor Less 380mA LDO with 1.2µAquicscent Current

In this paper a 380 mA low-dropout (LDO) regulator using an I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</inf> of only 1.2µA, with only0.5 nF capacitance for compensation. The LDO with dynamic biasing achieves a high unity gain frequency (UGF) of 10.6 MHz and maintains load transient response performance under 10% of output load voltage in both load conditions. Unlike other literatures this LDO does not have any buffer thus consumes very low power. The main block of this LDO is a rail to rail Operational Amplifier used as error amplifier which has three distinct parts: two complimentary differential amplifiers and one charging discharging amplifier. This rail to rail amplifier provides high swing to the power MOSFET which maintains the output irrespective of load current. Another important block that has been introduced here is overshoot and undershoot correction circuit that maintains a swift control over transient performance of the LDO circuit with only 1.2µA I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</inf>(quiescent current). The LDO is designed and simulated with 180nm CMOS process.

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Publication Details

Published
2024-11-30
DOI
https://doi.org/10.1109/edkcon62339.2024.10870797
Primary Topic
Semiconductor materials and devices
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article
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article

A Transient Enhanced Capacitor Less 380mA LDO with 1.2µAquicscent Current

Seema Mishra, Sayak Samanta, Swarnil Roy, Samiran Bandyopadhyay et al.
Semiconductor materials and devices
article

A Transient Enhanced Capacitor Less 380mA LDO with 1.2µAquicscent Current

Seema Mishra, Sayak Samanta, Swarnil Roy, Samiran Bandyopadhyay, J.J.M. Ferreira de
article en

Abstract

In this paper a 380 mA low-dropout (LDO) regulator using an I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</inf> of only 1.2µA, with only0.5 nF capacitance for compensation. The LDO with dynamic biasing achieves a high unity gain frequency (UGF) of 10.6 MHz and maintains load transient response performance under 10% of output load voltage in both load conditions. Unlike other literatures this LDO does not have any buffer thus consumes very low power. The main block of this LDO is a rail to rail Operational Amplifier used as error amplifier which has three distinct parts: two complimentary differential amplifiers and one charging discharging amplifier. This rail to rail amplifier provides high swing to the power MOSFET which maintains the output irrespective of load current. Another important block that has been introduced here is overshoot and undershoot correction circuit that maintains a swift control over transient performance of the LDO circuit with only 1.2µA I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</inf>(quiescent current). The LDO is designed and simulated with 180nm CMOS process.

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A Transient Enhanced Capacitor Less 380mA LDO with 1.2µAquicscent Current — Seema Mishra, Sayak Samanta, et al. · (2024) | TGRS Research Map | TGRS