Performance Analysis of Multiplexer Based Ternary Multiplier Designed Using FinFET Models

Multivalue logics, particularly ternary logic, offer enhanced energy efficiency and reduced circuit complexity, making them advantageous in digital system design. This article investigates the design and performance of a multiplexer-based ternary multiplier implemented using 18 nm FinFET technology. The study evaluates three distinct FinFET models: LVT, SVT and HVT. The performance of these models is assessed through power consumption, transient delay, and power-delay product (PDP). Simulation results reveal that the LVT, SVT, and HVT FinFET models exhibit power consumption values of 4.34 11W, 4.86 11Wand 4.29 11W, transient delays of 20.42 ns, 20.48 and 20.45 ns, and PDP values of 88.62, 99.53 and 87.73 (X10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−15</sup> J), respectively. This research contributes to the development of advanced VLSI systems, emphasizing the importance of selecting appropriate FinFET models to optimize the trade-offs between speed, power efficiency, and overall energy consumption in ternary logic circuits. Potential applications include memory systems, digital signal processing, quantum computing, and error detection and correction.