Analysis of Stress and Strain Dynamics in Sub-7nm GAA Si- and SiGe-Channel Nanosheet FETs

This work underscores the importance of stress/strain engineering in nanosheet FETs and provides a detailed explanation of the stress fields within a 3-stack Si and SiGe channel nanosheet FETs. The importance of stress management in silicon and SiGe-channel nanosheet FETs and a detailed quantification of the stress fields within these devices are discussed. A 3D numerical simulation study reveals that stress/strain engineering techniques can enhance the performance of Gate-all-around (GAA) vertically stacked nanosheet field-effect transistors (NSFETs) for 7 nm technology nodes. The choice between SiGe and/or Si channels ultimately depends on the specific application requirements, with SiGe being more suited for high-performance applications and Si being preferred for applications where reliability is paramount. This work has demonstrated the advantages of using multiple nanosheet stacks in strained-SiGe NSFETs.