CameraLink Interface Design Based on 3.5x Frequency Encoded Clock

Based on the EG4D20 FPGA chip of AnLogic Falcon series, this paper builds an image transmission platform with CameraLink interface, and proposes a CameraLink interface design scheme with low clock frequency requirements. Compared with the traditional implementation of the CameraLink interface of the LVDS transmitter chip, this design reduces power consumption and cost. Compared with the existing FPGA-based CameraLink interface IP, the proposed solution successfully optimizes the 7 -octave encoded clock to a 3.5-octave encoded clock, which increases the consumption of logic resources, but greatly reduces the clock frequency requirements of the CameraLink interface and the power consumption of the interface on the FPGA. The paper tests the pixel clock frequency of 85MHz, the prior art requires a 595MHz coded clock, and the design scheme only needs a 297.5MHz coded clock, and the power consumption of the former is 0.111W after the test of AnLogic power analysis tool, while the power consumption of the design scheme is 0.08W, and the power consumption is reduced by 27.9%.