Performance Analysis of a Heterojunction Dual Gate Ferroelectric Tunnel FET with Variation of Gate Stack Dielectric combination

In this study, a comparative analysis is performed based on SILVACO ATLAS TCAD for a Heterojunction Dual-Gate Ferroelectric Tunnel FET (HJ-DG-Fe-TFET) with different combinations of gate insulator oxide in buffer layer. To increase the device's ON current and minimize ambipolarity, a series combination of high-k and low-k oxide is utilized together with a ferroelectric layer beneath the gate. The intervention of negative capacitance caused by the ferroelectric layer results internal voltage amplification and hence enables the device to operate at low supply voltage, thereby reducing device power consumption. The addition of ferroelectric and high-k and low-k oxide layers to the gate stack decreased the gate stack's total effective capacitance, which in turn led to a smaller subthreshold swing, which is a crucial parameter for faster device switching. Limiting the ferroelectric layer thickness below its critical thickness results in hysteresis free operation of the device thereby making it suitable for logic operations. When compared to baseline TFETs, ferroelectric TFETs are viable candidates for energy-efficient low power applications in modern CMOS industry.