Performance Evaluation of Double Gate Junctionless Accumulation Mode Stacked Gate MOSFET

To continue the process of miniaturization and simultaneously to overcome the issues related to short channel effects, double gate junctionless accumulation mode stacked gate (DG-JLAMSG) MOSFET is proposed in the present piece of work. The DC, analog and RF performances are investigated with varying thickness of high-k gate stacking oxide. This structure has numerous advantage in improving the transconductance generation factor, cut-off frequency, linearity. Hence a detail investigation is needed to analyze the device behavior with respect to varying structural parameters. Presently, the performances of DG-JLAMSG are studied by changing the stack oxide thickness (TOXH). A remarkable improvement in performance is observed and the device can be a better contender for the designing of system on chip applications and RFICs.