Lateral Straggle Based Interface Trap Sensitivity in n-p-n SOI Double Gate TFETs

This article reports the impact of interface traps and dopant lateral straggle on a tunnel field-effect transistor (TFET) based on an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n-p-n$</tex> silicon body with a double-gate structure. Both gates are on the same side, spanning over two p-n junctions. In the proposed device, interface trap analysis is conducted considering a constant doping profile and an analytical doping profile having lateral straggle arising out of the ion implantation process. The article analyzes interface traps by considering variations in lateral straggle from 5 nm to 10 nm in the source and the drain regions. To realize localized interface traps, a framework involving segmented interface traps is adopted taking into account, lateral straggle in the source region. These analyses are systematically investigated through calibrated TCAD simulations with the objective of observing the impact of interface traps in both constant doping and analytical doping profiles.