Design of Power-Efficient Built-In Self-Repair for Interleaved Memory Systems

Trillions of memory cells are fabricated into the fingertip area of a semiconductor wafer. Therefore, it is almost impossible to ensure that there will be no defects after manufacturing. Various kinds of memory faults may arise after fabrication. Hard faults like, Stuck-at faults, address decoding faults, coupling faults as well as Soft faults also degrade the performance of a memory system. Recently Built-in Self-Test (BIST) and Built-in self-repair (BISR) mechanisms have been incorporated with the memory module to make it fault-tolerant. This paper proposes a power-efficient BISR architecture for interleaved memory to retain the system's reliability and increase the throughput. The proposed architecture consists of several redundant memory banks with an on-demand power-on feature which reduces power dissipation. HDL simulation of this work has been done using AMD Vivado and the proposed architecture is also implemented on FPGA (Spartan-7).