Investigating the Device and Circuit Level Performance of Nanoscale Double Gate Junctionless Transistors

The junctionless transistors (JLT) have been evolved as a device which is free from the need to fabricate the p-n junctions in semiconductor layer. In present work, the nanoscale double gate junctionless transistors have been designed with a physical gate length of 16 nm. The doping concentration and gate's work function of p-type device has been optimized to equate its threshold voltage with that of n-type JLT. The performance of both p-type and n-type JLTs have been observed and found that the devices reflect ON-current of the order of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{-4}\mathrm{A}/\mu \mathrm{m}$</tex>, OFF-current in the range of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{-9} \mathrm{A}/\text{um}$</tex>, ON/OFF current ratio of the order of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^5$</tex>.Furthermore, these devices have been used to implement an inverter circuit in Mixed-mode simulator of Silvaco technology computer aided tool (TCAD) which successfully reflects the voltage transfer characteristic. The implemented inverter successfully reflects the voltage transfer characteristics for various values of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{d}\mathrm{d}}$</tex> which enables these devices as an alternative of MOSFETs for low power circuit applications.