Investigation of FinFET with Multi-Channel Structures on Device Characteristics

The primary objective of this article is to investigate the device-level architecture and functionality of Fin field-effect transistors (FinFETs). Three distinct FinFET structures are analyzed, the standard or conventional FinFET, the Dual-Metal Gate FinFET, and the Dual-Fin FinFET. This research delves into the concept of dual or multi-Fin configurations, which introduce additional channels to the device. By enhancing gate control, these configurations aim to significantly improve the electrical performance of FinFETs. Detailed analyses of each structure will provide insights into their respective benefits and potential applications in advancing semiconductor technology. The Dual-Fin FinFET turns out to be superior in performance as it has a high drive-on current of (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>) = 3.34 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−4</sup> A and a lower off-state current of (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>) = 1.34 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−17</sup> A. Also, the sub-threshold slope (SS) is observed to be 48.43 mV/decade, compared to the other two structures such as conventional FinFET and Dual-Metal Gate FinFET. The software used for simulation is SILVACO TCAD (Technology Computer Aided Design).