Mapping Stress/Strain in Nanoscale FinFETs: Implications for Device Design
This paper presents a comprehensive study on the mapping of stress and strain in FinFETs and explores its implications for device performance. The investigation focuses on the characterization of stress and strain distribution in three-dimensional FinFET structures using advanced modeling and simulation techniques. The impact of stress and strain on device parameters such as carrier mobility, threshold voltage, and overall performance is analyzed in detail. The study highlights the importance of understanding the spatial distribution of stress and strain in FinFET devices and its influence on device behavior. Insights gained from this research can help in the optimization of FinFET design and fabrication processes to enhance device performance and reliability.
Authors
- C. K. Maiti (ORCID: https://orcid.org/0000-0003-2854-6606)
- Taraprasanna Dash (ORCID: https://orcid.org/0000-0001-6370-8573)
- J. Jena (ORCID: https://orcid.org/0000-0001-6964-5606)
- Devika Jena (ORCID: https://orcid.org/0000-0001-8615-0701)
- Subhashree Choudhury (ORCID: https://orcid.org/0000-0003-1872-7147)
- Κ. V. Subbarao
Institutions
- Chaitanya Bharathi Institute of Technology (IN)
- Siksha O Anusandhan University (IN)
Publication Details
- Published
- 2024-11-30
- DOI
- https://doi.org/10.1109/edkcon62339.2024.10870781
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00