ASIC Flow Implementation on a 32 Bit RISC V Processor using Cadence

This document portrays the design & ASIC flow implementation of a single-cycle microarchitecture of RV32I. RISC-V is chosen for its open-source ISA, which makes it accessible without any cost and offers similar capabilities as proprietary architectures like ARM and x86. The RV32I microarchitecture was designed using Verilog and comprises modules such as Instruction Fetch, Register Memory, Instruction Memory, ALU, and Control Unit. The functionality of the design was verified in Cadence Simvision tool, and it was compiled and elaborated in Cadence NClaunch tool. The design was synthesized error-free in Cadence Genus tool using TSMC 45nm technology libraries. The RTL design was validated by performing a Logic Equivalence Check (LEC) in Cadence LEC-Conformal tool, which verified that the design is perfectly mapped to gate-level netlist. Physical design was implemented in Cadence Innovus tool, and the timing of the design was verified in Cadence Tempus tool using the constraint files provided by TSMC 45nm technology.