Analog and High Frequency Analysis of Dielectric Pocket Engineered (DPE) 4H-SiC Based Dual Metal(DM), Gate-Stack (GS), ,Surrounding Gate, FET(DPE-4H-SiC-GSDM-SGFET) for GIDL Reduction

Gate induced drain leakages (GIDL) is a kind of short channel effects (SCEs) that can cause device damage due to persistent gate leakage of current. It acutely impairs the device's output, predominantly in analog utilizations. To reduce this effect, an innovative construction is projected with two dielectric-pockets close to the source region & drain region. This study examines a Dielectric Pocket Engineered, 4H-SiC Based Gate-Stack, Dual-Metal, Surrounding-Gate, FET (DPE-4H-SiC-GSDM-SGFET) for surface potential, electric field (contour), and subthreshold slope on several channel lengths (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}=50$</tex> nm,40 nm and 30 nm), A Gate-Stack with high-k based dielectric material, which includes Lanthanum oxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\text{La}_2 \mathrm{O}_3\right)$</tex> and Aluminum oxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\text{Al}_2 \mathrm{O}_3\right)$</tex>, have been employed. The objective is to reduce Gate-Induced Drain Leakage (GIDL) in off-state condition. Critical parameters such as drain current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\mathbf{I}_{\mathbf{d s}}\right)$</tex>, transconductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{gm})$</tex>, output cosductance (g<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf>), input capacitance (CGG) and cutoff frequency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\mathbf{f}_{\mathrm{T}}\right)$</tex> have been investigated. ATLAS 3-D simulator has been used for the simulation purpose.

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Published
2024-11-30
DOI
https://doi.org/10.1109/edkcon62339.2024.10870662
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1
Primary Topic
Silicon Carbide Semiconductor Technologies
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article
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Analog and High Frequency Analysis of Dielectric Pocket Engineered (DPE) 4H-SiC Based Dual Metal(DM), Gate-Stack (GS), ,Surrounding Gate, FET(DPE-4H-SiC-GSDM-SGFET) for GIDL Reduction

R.S. Gupta, Shobha Sharma, S. S. Deswal, Anubha Goel et al.
1 citations
Silicon Carbide Semiconductor Technologies
0.21
article

Analog and High Frequency Analysis of Dielectric Pocket Engineered (DPE) 4H-SiC Based Dual Metal(DM), Gate-Stack (GS), ,Surrounding Gate, FET(DPE-4H-SiC-GSDM-SGFET) for GIDL Reduction

R.S. Gupta, Shobha Sharma, S. S. Deswal, Anubha Goel, Sonam Rewari, Neeraj Neeraj
article en
1 citations

Abstract

Gate induced drain leakages (GIDL) is a kind of short channel effects (SCEs) that can cause device damage due to persistent gate leakage of current. It acutely impairs the device's output, predominantly in analog utilizations. To reduce this effect, an innovative construction is projected with two dielectric-pockets close to the source region & drain region. This study examines a Dielectric Pocket Engineered, 4H-SiC Based Gate-Stack, Dual-Metal, Surrounding-Gate, FET (DPE-4H-SiC-GSDM-SGFET) for surface potential, electric field (contour), and subthreshold slope on several channel lengths (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}=50$</tex> nm,40 nm and 30 nm), A Gate-Stack with high-k based dielectric material, which includes Lanthanum oxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\text{La}_2 \mathrm{O}_3\right)$</tex> and Aluminum oxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\text{Al}_2 \mathrm{O}_3\right)$</tex>, have been employed. The objective is to reduce Gate-Induced Drain Leakage (GIDL) in off-state condition. Critical parameters such as drain current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\mathbf{I}_{\mathbf{d s}}\right)$</tex>, transconductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{gm})$</tex>, output cosductance (g<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf>), input capacitance (CGG) and cutoff frequency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\mathbf{f}_{\mathrm{T}}\right)$</tex> have been investigated. ATLAS 3-D simulator has been used for the simulation purpose.

Maharaja Engineering College (IN), Indira Gandhi Delhi Technical University for Women (IN), Delhi Technological University (IN)
Openalex Percentile: Top 44%
Silicon Carbide Semiconductor Technologies
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