Optimizing Triple Material Staggered Heterojunction Double Gate MOSFET (TM-SH-DGMOS) Through Advanced Gate Engineering

This research paper emphasises on the simulation and analysis of Triple Material Staggered Heterojunction Double Gate MOSFET (TM-SH-DGMOSFET), with a focus on their possible uses in Radio Frequency (RF) and mixed-signal Systems-On-a-Chip (SoC). Using a numerical TCAD device simulator, the study examines the device's performance characteristics, particularly in Analog/RF and linearity contexts. The research investigates how variations in gate length ratios and gate materials influence key performance metrics, underscoring the potential benefits of these transistors for specific electronic applications. The research assesses multiple performance parameters for RF/Analog and linearity performance, including Transconductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathbf{g}_{\mathbf{m}})$</tex>, Transconductance Generation Factor (TGF), Cut-off Frequency (Ft), Gain Bandwidth Product (GBW), and Second Order Variable Intercept Point (VIP2), because of their better short channel effect (SCE) performance and manufacturability. The findings reveal that TM-SH-DGMOS devices exhibit promising characteristics, particularly in RF performance, when considering gate ratio variations, suggesting their competitiveness in low-power applications.