Comparative Performance Analysis of Dual FinFET and Gate-All-Around Triple Nanosheet FET for 5nm Node

This study presents a comparative performance analysis of FinFET and Gate-All-Around Nanosheet FET (NSFET) technologies at the 5nm node, focusing on their DC characteristics and device efficiency. Results demonstrate that NSFETs outperform FinFETs in several critical parameters. NSFETs exhibit a higher on-current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(I_{on})$</tex> of 88.57 µA compared to 64.35 µA for FinFETs, ensuring superior current driving capability and faster transistor switching. The leakage current (Ioff) of NSFETs is significantly lower (3.50 ×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–11</sup>A) compared to FinFETs (1.24 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–10</sup>A), leading to reduced power consumption and improved energy efficiency. The switching ratio <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(I_{on}/ I_{off)}$</tex> for NSFETs is 2.48 ×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup>, nearly five times higher than that of FinFETs, highlighting enhanced switching performance. NSFETs also exhibit a lower Subthreshold Slope (SS) of 67.94 mV/dec and a substantially reduced Drain-Induced Barrier Lowering (DIBL) of 15.69 mV/V, compared to 70.04 mV/dec and 43.11 mV/V for FinFETs, respectively. These improvements indicate superior gate control, reduced short-channel effects, and better scaling potential. The findings underscore the suitability of NSFETs for next-generation semiconductor applications, particularly in low-power, high-performance, and energy-efficient designs, positioning them as a robust alternative to FinFETs for advanced technology nodes.