High-Endurance Contention-Aware Power Optimized Hybrid Memory Using Clock Gating Memory

In the process of increasing the processor's performance heat has made it more difficult to increase frequency and thereby performance. As a solution, computer architecture has moved away from single-core chips and towards multi-core chips, sometimes called Chip Multiprocessors (CMPs). The last-level cache (LLC) in a coordinated multiprocessor (CMP) design is usually SRAM and is shared by numerous processors. There is an effort to optimize power consumption in the addressing system of the low-power SRAM delay buffer circuit shown in the design proposal. An array of novel power-saving strategies are included into the suggested SRAM addressing system. As the delay buffer operates in a sequential manner, it employs a ring-counter for addressing. A C-element gated-clock approach is proposed, and the operating frequency is reduced by half through the use of double-edge-triggered (DET) flip-flops in the ring counter. Additionally, to control the clock distribution throughout the network, a new gated-clock-driver tree is used in the design. To further reduce loading and power consumption, the memory block's input and output ports also use the gated-driver-tree approach. The proposed model uses optimistic address generation and a combination of SRAM and eDRAM for read/write operations of cache memory, ultimately reducing the dynamic power consumption by 20.43% and latency by around 23.45%.