Reliability Study of Interface Traps in Gate-All-Around Tunnel FET: A TCAD Simulation Approach

Threshold voltage hysteresis in transistor characteristics is common for CMOS device reliability. Scaling impacts electrostatic performance, prompting reliability analysis. A key check involves varying gate voltage sweeping frequency to observe hysteresis changes. This phenomenon is often not fully discussed. Our study focuses on trap charging/discharging at the silicon channel-insulator interface of gate-all-around tunnel field-effect transistors (GAA TFETs), using Silvaco ATLAS TCAD. We model interface traps causing threshold voltage instabilities, analyzing energy band diagrams, trap occupancy probability based on gate voltage, and its impact on transfer characteristics' sweep. We explore hysteresis changes across sweep frequencies, temperatures, and gate voltage ranges.