Design of T-Shape Tunnel FET with Enhanced Drain Current Characteristics at 30nm Technology

Conventional field-effect Transistors (FETs) exhibit suboptimal energy efficiency, whereas tunnel Field-Effect Transistors (TFETs) represent a novel category characterized by significantly enhanced efficiency. TFETs leverage a distinct quantum mechanical phenomenon for electron transportation, enabling operation at notably reduced voltage levels. Integration of TFETs with Complementary Metal-Oxide-Semiconductor (CMOS) technology holds the promise of substantially reducing power consumption in integrated circuits. The assessment of a novel transistor architecture's functionality hinged on an analysis of its electrical characteristics. The investigation revealed minimal leakage current during the off state (desirable) and efficient conduction in the on state (favorable). Notably, the transition between on and off states was found to be exceptionally precise. The research endeavor is centered on characterizing surface potential and electric field through the solution of Poisson's equation, employing a parabolic approximation technique for constructing an accurate device configuration. To affirm the validity of the proposed framework, the analytical outcomes are juxtaposed with data derived from Synopsys TCAD simulations.