Performance Analysis of Double-Gate Junctionless Tunnel FET with a Stepped Channel

In this article, we investigate a Junctionless TFET with a stepped channel (SJL-TFET) to demonstrate its superior ON-state current (ION), low subthreshold leakage current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>), and high current switching ratio (CSR) compared to conventional uniform JL-TFETs. Metals with appropriate work functions (Φ) are strategically placed above specific regions to induce charge carriers in the source and channel areas. Spacers are inserted between the source and gate metals to separate the source and channel regions. The proposed SJL-TFET device features a stepped gate structure, which optimizes the tunneling area and enhances the tunneling of carriers during the ON state. This design improvement leads to better device performance by achieving a more efficient carrier tunneling process. Performance metrics obtained from 2D-TCAD simulations show that the proposed SJL-TFET offers approximately a three-decade improvement in ON-state current and about a one-decade reduction in subthreshold leakage current. The enhanced DC characteristics of the SJL-TFET are primarily due to the improved tunneling efficiency facilitated by the stepped gate structure over the channel.