A µW Power CMOS Window Detector Circuit with Adjustable Thresholds for Low-Power Applications

An adjustable threshold CMOS window detector based on latch comparator is proposed here which compares between two DC threshold values. The threshold values are user adjustable. The window detector is based on a Pre-amplifier based latch comparator which is a significant part of the Analog to Digital converter (ADC). The proposed circuit is designed in SCL 180nm standard CMOS technology 1.8 V power supply. The window detector generates output with a maximum frequency of 18 MHz and 55ns delay. The proposed circuit uses a custom designed XOR gate which takes input from the comparator. The adjustable window length can be closer to supply <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{DD}$</tex> to Gnd. The total dynamic power consumption of the proposed circuit is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$32\mu \mathrm{W}$</tex>, which is less than some of the recently reported works.

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Publication Details

Published
2024-11-30
DOI
https://doi.org/10.1109/edkcon62339.2024.10870773
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

A µW Power CMOS Window Detector Circuit with Adjustable Thresholds for Low-Power Applications

A. Dash, Koyel Mukherjee, Soham Banerjee, Soumya Pandit et al.
Analog and Mixed-Signal Circuit Design
article

A µW Power CMOS Window Detector Circuit with Adjustable Thresholds for Low-Power Applications

A. Dash, Koyel Mukherjee, Soham Banerjee, Soumya Pandit, Uday Sannigrahi
article en

Abstract

An adjustable threshold CMOS window detector based on latch comparator is proposed here which compares between two DC threshold values. The threshold values are user adjustable. The window detector is based on a Pre-amplifier based latch comparator which is a significant part of the Analog to Digital converter (ADC). The proposed circuit is designed in SCL 180nm standard CMOS technology 1.8 V power supply. The window detector generates output with a maximum frequency of 18 MHz and 55ns delay. The proposed circuit uses a custom designed XOR gate which takes input from the comparator. The adjustable window length can be closer to supply <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{DD}$</tex> to Gnd. The total dynamic power consumption of the proposed circuit is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$32\mu \mathrm{W}$</tex>, which is less than some of the recently reported works.

University of Calcutta (IN)
Affordable and clean energy
Openalex Percentile: Top 76%
Analog and Mixed-Signal Circuit Design
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