Demonstration of High Transconductance Gate-All-Around Transistors Using Negative Capacitance ‘Super High-K’ Gate Stack

We demonstrate a gate all around (GAA) negative capacitance FET (NCFET). The device provides an equivalent oxide thickness (EOT) of 6.5Å with unscavenged SiO2 interlayer (IL), and a high transconductance of 2.15 mS/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m for L<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${_{\text {eff}}} =45$ </tex-math></inline-formula> nm, matching and exceeding what has been reported for MOSFETs with much shorter gate lengths and similar gate stack thickness. Our results demonstrate feasibility of negative capacitance gate stack in a GAA geometry for enhanced gate control, scaling, and performance.

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Publication Details

Journal
IEEE Electron Device Letters
Published
2025-02-13
DOI
https://doi.org/10.1109/led.2025.3541547
Citations
2
Primary Topic
Semiconductor materials and devices
Type
article
Field-Weighted Citation Impact
1.46

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article

Demonstration of High Transconductance Gate-All-Around Transistors Using Negative Capacitance ‘Super High-K’ Gate Stack

Suraj Cheema, Urmita Sikder, Chia-Chun Lee, Chenming Hu et al.
2 citations
IEEE Electron Device Letters
Semiconductor materials and devices
1.46
article

Demonstration of High Transconductance Gate-All-Around Transistors Using Negative Capacitance ‘Super High-K’ Gate Stack

Suraj Cheema, Urmita Sikder, Chia-Chun Lee, Chenming Hu, Chirag Garg, A. Varma, Sayeef Salahuddin, Nirmaan Shanker, Li‐Chen Wang, Shang‐Lin Hsu, Jong Ho Park
article en
2 citations

Abstract

We demonstrate a gate all around (GAA) negative capacitance FET (NCFET). The device provides an equivalent oxide thickness (EOT) of 6.5Å with unscavenged SiO2 interlayer (IL), and a high transconductance of 2.15 mS/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m for L<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${_{\text {eff}}} =45$ </tex-math></inline-formula> nm, matching and exceeding what has been reported for MOSFETs with much shorter gate lengths and similar gate stack thickness. Our results demonstrate feasibility of negative capacitance gate stack in a GAA geometry for enhanced gate control, scaling, and performance.

IEEE Electron Device LettersVol. 46(4)
Intel (United States) (US), Massachusetts Institute of Technology (US), University of California, Berkeley (US)
Defense Threat Reduction Agency
Affordable and clean energy
Openalex Percentile: Top 19%
Semiconductor materials and devices
1.46
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