Demonstration of High Transconductance Gate-All-Around Transistors Using Negative Capacitance ‘Super High-K’ Gate Stack
We demonstrate a gate all around (GAA) negative capacitance FET (NCFET). The device provides an equivalent oxide thickness (EOT) of 6.5Å with unscavenged SiO2 interlayer (IL), and a high transconductance of 2.15 mS/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m for L<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${_{\text {eff}}} =45$ </tex-math></inline-formula> nm, matching and exceeding what has been reported for MOSFETs with much shorter gate lengths and similar gate stack thickness. Our results demonstrate feasibility of negative capacitance gate stack in a GAA geometry for enhanced gate control, scaling, and performance.
Authors
- Suraj Cheema (ORCID: https://orcid.org/0000-0001-5878-3624)
- Urmita Sikder (ORCID: https://orcid.org/0000-0002-1248-7835)
- Chia-Chun Lee
- Chenming Hu (ORCID: https://orcid.org/0000-0003-0836-6296)
- Chirag Garg (ORCID: https://orcid.org/0000-0003-4897-1802)
- A. Varma (ORCID: https://orcid.org/0009-0009-3117-4517)
- Sayeef Salahuddin (ORCID: https://orcid.org/0000-0002-0315-2208)
- Nirmaan Shanker (ORCID: https://orcid.org/0000-0002-4102-9665)
- Li‐Chen Wang (ORCID: https://orcid.org/0000-0003-0703-5030)
- Shang‐Lin Hsu (ORCID: https://orcid.org/0000-0003-1158-9685)
- Jong Ho Park (ORCID: https://orcid.org/0009-0008-8143-4690)
Institutions
- Intel (United States) (US)
- Massachusetts Institute of Technology (US)
- University of California, Berkeley (US)
Publication Details
- Journal
- IEEE Electron Device Letters
- Published
- 2025-02-13
- DOI
- https://doi.org/10.1109/led.2025.3541547
- Citations
- 2
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 1.46
Funders
- Defense Threat Reduction Agency