FPGA Implementation of Image Encryption by Adopting New Shimizu–Morioka System-Based Chaos Synchronization

This study presents an innovative approach utilizing the new Shimizu–Morioka chaotic system. By integrating adaptive backstepping control with GYC partial region stability theory, we successfully achieve synchronization of a slave system with the proposed Shimizu–Morioka chaotic system. The architecture, encompassing the chaotic master system, synchronized slave system, adaptive backstepping controllers, and parameter update laws, has been implemented on an FPGA platform. Comparative analysis demonstrates that the synchronization convergence times (e1, e2, e3, and e4) are significantly reduced compared to conventional adaptive backstepping control methods, exhibiting speed enhancements of approximately 3.42, 3.55, 5.89, and 9.23 times for e1, e2, e3, and e4, respectively. Furthermore, the synchronization results obtained from continuous-time, discrete-time systems, and FPGA implementations exhibit consistent outcomes, validating the effectiveness of the proposed model and controller. Leveraging this validated synchronization framework, chaotic synchronization and secure image encryption are successfully implemented on the FPGA platform. The chaotic signal circuits are meticulously designed and integrated into the FPGA to facilitate a robust image encryption algorithm. In this system, digital signals generated by the synchronized slave chaotic system are utilized for image decryption, while the master chaotic system’s digital signals are employed for encryption. This dual-system architecture highlights the efficacy of the chaotic synchronization method based on the novel Shimizu–Morioka system for practical applications in secure communication.