MultiPoint: Enabling scalable pre-silicon performance evaluation for multi-task workloads
With the core numbers integrated within single processors growing and the fast development of cloud computing, performance evaluation for multi-core systems is increasingly crucial. It is typically conducted by executing multi-task workloads, exemplified by SPEC CPU Rate, to measure metrics like system’s throughput. In response, several sampling-based methods have been developed for their pre-silicon performance evaluation. Nevertheless, these methods involve directly capturing multi-task checkpoints, which presents scalability issues of significant storage and time overheads. Therefore, enabling more scalable performance evaluation remains a critical problem. In this work, we propose MultiPoint to enable scalable pre-silicon performance evaluation for multi-task workloads. It is noted that in the multi-task workloads of interest, each task executes independently without inter-task communication. Therefore, MultiPoint is motivated to construct the required multi-task checkpoints by recovering multiple single-task checkpoints across different cores and guarantee their smooth execution through address remapping and shuffling. We implemented MultiPoint on the Emulator Accelerator and assessed its evaluation accuracy against its post-silicon Loongson 3A6000 processor. Using SPEC CPU 2017 as the benchmark, MultiPoint achieved the estimation errors of 6.20%, 5.45%, and 6.99% for Rate 2, Rate 4, and Rate 8, respectively, achieving comparable accuracy compared to direct multi-task checkpointing but in a more scalable manner with substantially 86.0% lower storage and 93.7% less time overheads. • We proposed MultiPoint to compose multi-task checkpoints through the combination of multiple single-task checkpoints, which enables agile pre-silicon performance evaluation for multi-task workloads. • We implemented the evaluation routine of MultiPoint on the Emulator Accelerator and assessed its performance evaluation accuracy against its post-silicon Loongson 3A6000 commercial processor. • We evaluated MultiPoint on the SPEC CPU 2017 Rate benchmark. MultiPoint achieved the score estimation errors of 6.20%, 5.45%, and 6.99% for Rate 2, Rate 4, and Rate 8, respectively, achieving comparable estimation accuracy compared to the direct multi-task checkpointing but in a more agile manner.
Authors
- Xinyu Li (ORCID: https://orcid.org/0000-0002-2640-8173)
- Wenxiang Wang (ORCID: https://orcid.org/0000-0001-8797-1413)
- Weitong Wang (ORCID: https://orcid.org/0000-0002-3481-3670)
- Fuxin Zhang (ORCID: https://orcid.org/0000-0003-0430-3669)
- Feng Xue
- Chenji Han (ORCID: https://orcid.org/0009-0007-1247-9644)
Institutions
- Institute of Computing Technology (CN)
- University of Chinese Academy of Sciences (CN)
Publication Details
- Journal
- BenchCouncil Transactions on Benchmarks Standards and Evaluations
- Published
- 2024-09-01
- DOI
- https://doi.org/10.1016/j.tbench.2025.100189
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00